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added addressing modes

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This commit is contained in:
Lauchmelder 2021-10-22 16:39:48 +02:00
parent 458500bd59
commit 0f62079193
3 changed files with 364 additions and 108 deletions
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119
NES Emulator/cpu.c
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@ -48,15 +48,132 @@ void fetch(struct CPU* cpu)
Byte opcodeVal = readBus(cpu->bus, cpu->pc);
cpu->currentOpcode = OPCODE_TABLE + opcodeVal;
if (cpu->currentOpcode->op == Unknown)
if (cpu->currentOpcode->op == XXX)
{
fprintf(stderr, "Unknown opcode: %x", opcodeVal);
exit(1);
}
cpu->remainingCycles = cpu->currentOpcode->cycles;
switch (cpu->currentOpcode->addr)
{
case ACC:
cpu->fetchedVal = cpu->acc;
break;
case ABS:
{
Byte lo = readBus(cpu->bus, cpu->pc++);
Byte hi = readBus(cpu->bus, cpu->pc++);
cpu->fetchedAddress = ((Word)hi << 8) | lo;
} break;
case ABX:
{
Byte lo = readBus(cpu->bus, cpu->pc++);
Byte hi = readBus(cpu->bus, cpu->pc++);
Word addr = ((Word)hi << 8) | lo;
cpu->fetchedAddress = addr + cpu->x;
if ((cpu->fetchedAddress & 0xFF00) != (addr & 0xFF00))
cpu->remainingCycles++;
} break;
case ABY:
{
Byte lo = readBus(cpu->bus, cpu->pc++);
Byte hi = readBus(cpu->bus, cpu->pc++);
Word addr = ((Word)hi << 8) | lo;
cpu->fetchedAddress = addr + cpu->y;
if ((cpu->fetchedAddress & 0xFF00) != (addr & 0xFF00))
cpu->remainingCycles++;
} break;
case IMM:
cpu->fetchedVal = readBus(cpu->bus, cpu->pc++);
break;
case IMP:
break;
case IND:
{
Byte lo = readBus(cpu->bus, cpu->pc++);
Byte hi = readBus(cpu->bus, cpu->pc++);
Word addr = ((Word)hi << 8) | lo;
cpu->fetchedAddress = readBus(cpu->bus, addr);
} break;
case INDX:
{
Byte op = readBus(cpu->bus, cpu->pc++);
Byte lo = readBus(cpu->bus, op + cpu->x);
Byte hi = readBus(cpu->bus, op + cpu->x + 1);
Word addr = ((Word)hi << 8) | lo;
cpu->fetchedAddress = readBus(cpu->bus, addr);
} break;
case INDY:
{
Byte op = readBus(cpu->bus, cpu->pc++);
Byte lo = readBus(cpu->bus, op);
Byte hi = readBus(cpu->bus, op + 1);
Word addr = ((Word)hi << 8) | lo;
addr = readBus(cpu->bus, addr);
cpu->fetchedAddress = addr + cpu->y;
if ((cpu->fetchedAddress & 0xFF00) != (addr & 0xFF00))
cpu->remainingCycles++;
} break;
case REL:
{
cpu->fetchedRelAddress = readBus(cpu->bus, cpu->pc++);
} break;
case ZPG:
cpu->fetchedAddress = readBus(cpu->bus, cpu->pc++);
break;
case ZPX:
{
cpu->fetchedAddress = readBus(cpu->bus, cpu->pc++) + cpu->x;
cpu->fetchedAddress |= 0xFF;
} break;
case ZPY:
{
cpu->fetchedAddress = readBus(cpu->bus, cpu->pc++) + cpu->y;
cpu->fetchedAddress |= 0xFF;
} break;
}
}
void execute(struct CPU* cpu)
{
switch (cpu->currentOpcode->op)
{
case JMP:
{
cpu->pc = cpu->fetchedAddress;
} break;
default:
fprintf(stderr, "Unknown instruction: %s", cpu->currentOpcode->str);
exit(1);
break;
}
}