added addressing modes
This commit is contained in:
Lauchmelder
parent
458500bd59
commit
0f62079193
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@ -48,15 +48,132 @@ void fetch(struct CPU* cpu)
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Byte opcodeVal = readBus(cpu->bus, cpu->pc);
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cpu->currentOpcode = OPCODE_TABLE + opcodeVal;
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if (cpu->currentOpcode->op == Unknown)
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if (cpu->currentOpcode->op == XXX)
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{
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fprintf(stderr, "Unknown opcode: %x", opcodeVal);
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exit(1);
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}
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cpu->remainingCycles = cpu->currentOpcode->cycles;
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switch (cpu->currentOpcode->addr)
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{
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case ACC:
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cpu->fetchedVal = cpu->acc;
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break;
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case ABS:
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{
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Byte lo = readBus(cpu->bus, cpu->pc++);
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Byte hi = readBus(cpu->bus, cpu->pc++);
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cpu->fetchedAddress = ((Word)hi << 8) | lo;
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} break;
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case ABX:
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{
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Byte lo = readBus(cpu->bus, cpu->pc++);
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Byte hi = readBus(cpu->bus, cpu->pc++);
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Word addr = ((Word)hi << 8) | lo;
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cpu->fetchedAddress = addr + cpu->x;
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if ((cpu->fetchedAddress & 0xFF00) != (addr & 0xFF00))
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cpu->remainingCycles++;
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} break;
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case ABY:
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{
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Byte lo = readBus(cpu->bus, cpu->pc++);
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Byte hi = readBus(cpu->bus, cpu->pc++);
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Word addr = ((Word)hi << 8) | lo;
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cpu->fetchedAddress = addr + cpu->y;
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if ((cpu->fetchedAddress & 0xFF00) != (addr & 0xFF00))
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cpu->remainingCycles++;
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} break;
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case IMM:
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cpu->fetchedVal = readBus(cpu->bus, cpu->pc++);
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break;
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case IMP:
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break;
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case IND:
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{
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Byte lo = readBus(cpu->bus, cpu->pc++);
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Byte hi = readBus(cpu->bus, cpu->pc++);
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Word addr = ((Word)hi << 8) | lo;
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cpu->fetchedAddress = readBus(cpu->bus, addr);
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} break;
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case INDX:
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{
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Byte op = readBus(cpu->bus, cpu->pc++);
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Byte lo = readBus(cpu->bus, op + cpu->x);
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Byte hi = readBus(cpu->bus, op + cpu->x + 1);
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Word addr = ((Word)hi << 8) | lo;
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cpu->fetchedAddress = readBus(cpu->bus, addr);
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} break;
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case INDY:
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{
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Byte op = readBus(cpu->bus, cpu->pc++);
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Byte lo = readBus(cpu->bus, op);
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Byte hi = readBus(cpu->bus, op + 1);
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Word addr = ((Word)hi << 8) | lo;
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addr = readBus(cpu->bus, addr);
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cpu->fetchedAddress = addr + cpu->y;
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if ((cpu->fetchedAddress & 0xFF00) != (addr & 0xFF00))
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cpu->remainingCycles++;
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} break;
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case REL:
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{
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cpu->fetchedRelAddress = readBus(cpu->bus, cpu->pc++);
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} break;
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case ZPG:
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cpu->fetchedAddress = readBus(cpu->bus, cpu->pc++);
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break;
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case ZPX:
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{
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cpu->fetchedAddress = readBus(cpu->bus, cpu->pc++) + cpu->x;
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cpu->fetchedAddress |= 0xFF;
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} break;
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case ZPY:
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{
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cpu->fetchedAddress = readBus(cpu->bus, cpu->pc++) + cpu->y;
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cpu->fetchedAddress |= 0xFF;
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} break;
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}
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}
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void execute(struct CPU* cpu)
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{
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switch (cpu->currentOpcode->op)
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{
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case JMP:
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{
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cpu->pc = cpu->fetchedAddress;
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} break;
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default:
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fprintf(stderr, "Unknown instruction: %s", cpu->currentOpcode->str);
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exit(1);
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break;
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}
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}
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@ -5,7 +5,7 @@
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struct Bus;
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typedef enum
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enum Operation
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{
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XXX = 0,
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ADC, AND, ASL, BCC, BCS, BEQ, BIT, BMI,
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@ -15,23 +15,23 @@ typedef enum
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LSR, NOP, ORA, PHA, PHP, PLA, PLP, ROL,
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ROR, RTI, RTS, SBC, SEC, SED, SEI, STA,
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STX, STY, TAX, TAY, TSX, TXA, TXS, TYA
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} Operation;
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};
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typedef enum
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enum AddrMode
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{
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ACC, ABS, ABX, ABY, IMM, IMP, IND, XIN, INY, REL, ZPG, ZPX, ZPY
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} AddrMode;
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ACC, ABS, ABX, ABY, IMM, IMP, IND, INDX, INDY, REL, ZPG, ZPX, ZPY
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};
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struct Opcode
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{
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Operation op;
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AddrMode addr;
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enum Operation op;
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enum AddrMode addr;
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Byte cycles;
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const char str[4];
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};
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const struct Opcode OPCODE_MATRIX[512];
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const struct Opcode OPCODE_TABLE[256];
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struct CPU
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@ -59,8 +59,11 @@ struct CPU
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Word pc;
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Byte remainingCycles;
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Byte fetchedVal;
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Word fetchedAddress;
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char fetchedRelAddress;
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const struct Opcode* currentOpcode;
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struct Bus* bus;
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@ -5,7 +5,7 @@
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const struct Opcode OPCODE_TABLE[256] =
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{
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/* 00 */ NEW_OPCODE(BRK, IMP, 7),
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/* 01 */ NEW_OPCODE(ORA, XIN, 6),
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/* 01 */ NEW_OPCODE(ORA, INDX, 6),
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/* 02 */ NEW_OPCODE(XXX, IMP, 0),
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/* 03 */ NEW_OPCODE(XXX, IMP, 0),
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/* 04 */ NEW_OPCODE(XXX, IMP, 0),
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@ -22,7 +22,7 @@ const struct Opcode OPCODE_TABLE[256] =
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/* 0F */ NEW_OPCODE(XXX, IMP, 0),
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/* 10 */ NEW_OPCODE(BPL, REL, 2),
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/* 11 */ NEW_OPCODE(ORA, INY, 5),
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/* 11 */ NEW_OPCODE(ORA, INDY, 5),
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/* 12 */ NEW_OPCODE(XXX, IMP, 0),
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/* 13 */ NEW_OPCODE(XXX, IMP, 0),
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/* 14 */ NEW_OPCODE(XXX, IMP, 0),
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@ -38,105 +38,241 @@ const struct Opcode OPCODE_TABLE[256] =
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/* 1E */ NEW_OPCODE(ASL, ABX, 7),
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/* 1F */ NEW_OPCODE(XXX, IMP, 0),
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///* 20 */ NEW_OPCODE(JSR, ABS),
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///* 21 */ NEW_OPCODE(AND, XIN),
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///* 22 */ NEW_OPCODE(XXX, IMP),
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///* 23 */ NEW_OPCODE(XXX, IMP),
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///* 24 */ NEW_OPCODE(BIT, ZPG),
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///* 25 */ NEW_OPCODE(AND, ZPG),
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///* 26 */ NEW_OPCODE(ROL, ZPG),
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///* 27 */ NEW_OPCODE(XXX, IMP),
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///* 28 */ NEW_OPCODE(PLP, IMP),
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///* 29 */ NEW_OPCODE(AND, IMM),
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///* 2A */ NEW_OPCODE(ROL, ACC),
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///* 2B */ NEW_OPCODE(XXX, IMP),
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///* 2C */ NEW_OPCODE(BIT, ABS),
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///* 2D */ NEW_OPCODE(AND, ABS),
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///* 2E */ NEW_OPCODE(ROL, ABS),
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///* 2F */ NEW_OPCODE(XXX, IMP),
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/* 20 */ NEW_OPCODE(JSR, ABS, 6),
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/* 21 */ NEW_OPCODE(AND, INDX, 6),
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/* 22 */ NEW_OPCODE(XXX, IMP, 0),
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/* 23 */ NEW_OPCODE(XXX, IMP, 0),
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/* 24 */ NEW_OPCODE(BIT, ZPG, 3),
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/* 25 */ NEW_OPCODE(AND, ZPG, 3),
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/* 26 */ NEW_OPCODE(ROL, ZPG, 5),
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/* 27 */ NEW_OPCODE(XXX, IMP, 0),
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/* 28 */ NEW_OPCODE(PLP, IMP, 4),
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/* 29 */ NEW_OPCODE(AND, IMM, 2),
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/* 2A */ NEW_OPCODE(ROL, ACC, 2),
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/* 2B */ NEW_OPCODE(XXX, IMP, 0),
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/* 2C */ NEW_OPCODE(BIT, ABS, 4),
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/* 2D */ NEW_OPCODE(AND, ABS, 4),
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/* 2E */ NEW_OPCODE(ROL, ABS, 6),
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/* 2F */ NEW_OPCODE(XXX, IMP, 0),
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///* 30 */ NEW_OPCODE(BMI, REL),
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///* 31 */ NEW_OPCODE(AND, INY),
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///* 32 */ NEW_OPCODE(XXX, IMP),
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///* 33 */ NEW_OPCODE(XXX, IMP),
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///* 34 */ NEW_OPCODE(XXX, IMP),
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///* 35 */ NEW_OPCODE(AND, ZPX),
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///* 36 */ NEW_OPCODE(ROL, ZPX),
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///* 37 */ NEW_OPCODE(XXX, IMP),
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///* 38 */ NEW_OPCODE(SEC, IMP),
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///* 39 */ NEW_OPCODE(AND, ABY),
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///* 3A */ NEW_OPCODE(XXX, IMP),
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///* 3B */ NEW_OPCODE(XXX, IMP),
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///* 3C */ NEW_OPCODE(XXX, IMP),
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///* 3D */ NEW_OPCODE(AND, ABX),
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///* 3E */ NEW_OPCODE(ROL, ABX),
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///* 3F */ NEW_OPCODE(XXX, IMP),
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/* 30 */ NEW_OPCODE(BMI, REL, 2),
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/* 31 */ NEW_OPCODE(AND, INDY, 5),
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/* 32 */ NEW_OPCODE(XXX, IMP, 0),
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/* 33 */ NEW_OPCODE(XXX, IMP, 0),
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/* 34 */ NEW_OPCODE(XXX, IMP, 0),
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/* 35 */ NEW_OPCODE(AND, ZPX, 4),
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/* 36 */ NEW_OPCODE(ROL, ZPX, 6),
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/* 37 */ NEW_OPCODE(XXX, IMP, 0),
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/* 38 */ NEW_OPCODE(SEC, IMP, 2),
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/* 39 */ NEW_OPCODE(AND, ABY, 4),
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/* 3A */ NEW_OPCODE(XXX, IMP, 0),
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/* 3B */ NEW_OPCODE(XXX, IMP, 0),
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/* 3C */ NEW_OPCODE(XXX, IMP, 0),
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/* 3D */ NEW_OPCODE(AND, ABX, 4),
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/* 3E */ NEW_OPCODE(ROL, ABX, 7),
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/* 3F */ NEW_OPCODE(XXX, IMP, 0),
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///* 40 */ NEW_OPCODE(RTI, IMP),
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///* 41 */ NEW_OPCODE(EOR, XIN),
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///* 42 */ NEW_OPCODE(XXX, IMP),
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///* 43 */ NEW_OPCODE(XXX, IMP),
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///* 44 */ NEW_OPCODE(XXX, IMP),
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///* 45 */ NEW_OPCODE(EOR, ZPG),
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///* 46 */ NEW_OPCODE(LSR, ZPG),
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///* 47 */ NEW_OPCODE(XXX, IMP),
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///* 48 */ NEW_OPCODE(PHA, IMP),
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///* 49 */ NEW_OPCODE(EOR, IMM),
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///* 4A */ NEW_OPCODE(LSR, ACC),
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///* 4B */ NEW_OPCODE(XXX, IMP),
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///* 4C */ NEW_OPCODE(JMP, ABS),
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///* 4D */ NEW_OPCODE(EOR, ABS),
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///* 4E */ NEW_OPCODE(LSR, ABS),
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///* 4F */ NEW_OPCODE(XXX, IMP),
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/* 40 */ NEW_OPCODE(RTI, IMP, 6),
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/* 41 */ NEW_OPCODE(EOR, INDX, 6),
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/* 42 */ NEW_OPCODE(XXX, IMP, 0),
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/* 43 */ NEW_OPCODE(XXX, IMP, 0),
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/* 44 */ NEW_OPCODE(XXX, IMP, 0),
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/* 45 */ NEW_OPCODE(EOR, ZPG, 3),
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/* 46 */ NEW_OPCODE(LSR, ZPG, 5),
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/* 47 */ NEW_OPCODE(XXX, IMP, 0),
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/* 48 */ NEW_OPCODE(PHA, IMP, 3),
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/* 49 */ NEW_OPCODE(EOR, IMM, 2),
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/* 4A */ NEW_OPCODE(LSR, ACC, 2),
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/* 4B */ NEW_OPCODE(XXX, IMP, 0),
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/* 4C */ NEW_OPCODE(JMP, ABS, 3),
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/* 4D */ NEW_OPCODE(EOR, ABS, 4),
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/* 4E */ NEW_OPCODE(LSR, ABS, 6),
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/* 4F */ NEW_OPCODE(XXX, IMP, 0),
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///* 50 */ NEW_OPCODE(BVC, REL),
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///* 51 */ NEW_OPCODE(EOR, INY),
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///* 52 */ NEW_OPCODE(XXX, IMP),
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///* 53 */ NEW_OPCODE(XXX, IMP),
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///* 54 */ NEW_OPCODE(XXX, IMP),
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///* 55 */ NEW_OPCODE(EOR, ZPX),
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///* 56 */ NEW_OPCODE(LSR, ZPX),
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///* 57 */ NEW_OPCODE(XXX, IMP),
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///* 58 */ NEW_OPCODE(CLI, IMP),
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///* 59 */ NEW_OPCODE(EOR, ABY),
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///* 5A */ NEW_OPCODE(XXX, IMP),
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///* 5B */ NEW_OPCODE(XXX, IMP),
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///* 5C */ NEW_OPCODE(XXX, IMP),
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///* 5D */ NEW_OPCODE(EOR, ABX),
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///* 5E */ NEW_OPCODE(LSR, ABX),
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///* 5F */ NEW_OPCODE(XXX, IMP),
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/* 50 */ NEW_OPCODE(BVC, REL, 2),
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/* 51 */ NEW_OPCODE(EOR, INDY, 5),
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/* 52 */ NEW_OPCODE(XXX, IMP, 0),
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/* 53 */ NEW_OPCODE(XXX, IMP, 0),
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/* 54 */ NEW_OPCODE(XXX, IMP, 0),
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/* 55 */ NEW_OPCODE(EOR, ZPX, 4),
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/* 56 */ NEW_OPCODE(LSR, ZPX, 6),
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/* 57 */ NEW_OPCODE(XXX, IMP, 0),
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/* 58 */ NEW_OPCODE(CLI, IMP, 2),
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/* 59 */ NEW_OPCODE(EOR, ABY, 4),
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/* 5A */ NEW_OPCODE(XXX, IMP, 0),
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/* 5B */ NEW_OPCODE(XXX, IMP, 0),
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/* 5C */ NEW_OPCODE(XXX, IMP, 0),
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/* 5D */ NEW_OPCODE(EOR, ABX, 4),
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/* 5E */ NEW_OPCODE(LSR, ABX, 7),
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/* 5F */ NEW_OPCODE(XXX, IMP, 0),
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///* 60 */ NEW_OPCODE(RTS, IMP),
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///* 61 */ NEW_OPCODE(ADC, XIN),
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///* 62 */ NEW_OPCODE(XXX, IMP),
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///* 63 */ NEW_OPCODE(XXX, IMP),
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///* 64 */ NEW_OPCODE(XXX, IMP),
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///* 65 */ NEW_OPCODE(ADC, ZPG),
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///* 66 */ NEW_OPCODE(ROR, ZPG),
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///* 67 */ NEW_OPCODE(XXX, IMP),
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///* 68 */ NEW_OPCODE(PLA, IMP),
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///* 69 */ NEW_OPCODE(ADC, IMM),
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///* 6A */ NEW_OPCODE(ROR, ACC),
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///* 6B */ NEW_OPCODE(XXX, IMP),
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///* 6C */ NEW_OPCODE(JMP, IND),
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///* 6D */ NEW_OPCODE(ADC, ABS),
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///* 6E */ NEW_OPCODE(ROR, ABS),
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///* 6F */ NEW_OPCODE(XXX, IMP),
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/* 60 */ NEW_OPCODE(RTS, IMP, 6),
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/* 61 */ NEW_OPCODE(ADC, INDX, 6),
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/* 62 */ NEW_OPCODE(XXX, IMP, 0),
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/* 63 */ NEW_OPCODE(XXX, IMP, 0),
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/* 64 */ NEW_OPCODE(XXX, IMP, 0),
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/* 65 */ NEW_OPCODE(ADC, ZPG, 3),
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/* 66 */ NEW_OPCODE(ROR, ZPG, 5),
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/* 67 */ NEW_OPCODE(XXX, IMP, 0),
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/* 68 */ NEW_OPCODE(PLA, IMP, 4),
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/* 69 */ NEW_OPCODE(ADC, IMM, 2),
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/* 6A */ NEW_OPCODE(ROR, ACC, 2),
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/* 6B */ NEW_OPCODE(XXX, IMP, 0),
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/* 6C */ NEW_OPCODE(JMP, IND, 5),
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/* 6D */ NEW_OPCODE(ADC, ABS, 4),
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/* 6E */ NEW_OPCODE(ROR, ABS, 6),
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/* 6F */ NEW_OPCODE(XXX, IMP, 0),
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///* 70 */ NEW_OPCODE(BVS, REL),
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///* 71 */ NEW_OPCODE(ADC, INY),
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///* 72 */ NEW_OPCODE(XXX, IMP),
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///* 73 */ NEW_OPCODE(XXX, IMP),
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///* 74 */ NEW_OPCODE(XXX, IMP),
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///* 75 */ NEW_OPCODE(ADC, ZPX),
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///* 76 */ NEW_OPCODE(ROR, ZPX),
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///* 77 */ NEW_OPCODE(XXX, IMP),
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///* 78 */ NEW_OPCODE(SEI, IMP),
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///* 79 */ NEW_OPCODE(ADC, ABY),
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///* 7A */ NEW_OPCODE(XXX, IMP),
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///* 7B */ NEW_OPCODE(XXX, IMP),
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///* 7C */ NEW_OPCODE(XXX, IMP),
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///* 7D */ NEW_OPCODE(ADC, ABX),
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///* 7E */ NEW_OPCODE(ROR, ABX),
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///* 7F */ NEW_OPCODE(XXX, IMP),
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}
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/* 70 */ NEW_OPCODE(BVS, REL, 2),
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/* 71 */ NEW_OPCODE(ADC, INDY, 5),
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/* 72 */ NEW_OPCODE(XXX, IMP, 0),
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/* 73 */ NEW_OPCODE(XXX, IMP, 0),
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/* 74 */ NEW_OPCODE(XXX, IMP, 0),
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/* 75 */ NEW_OPCODE(ADC, ZPX, 4),
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/* 76 */ NEW_OPCODE(ROR, ZPX, 6),
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/* 77 */ NEW_OPCODE(XXX, IMP, 0),
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/* 78 */ NEW_OPCODE(SEI, IMP, 2),
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/* 79 */ NEW_OPCODE(ADC, ABY, 4),
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/* 7A */ NEW_OPCODE(XXX, IMP, 0),
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/* 7B */ NEW_OPCODE(XXX, IMP, 0),
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/* 7C */ NEW_OPCODE(XXX, IMP, 0),
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/* 7D */ NEW_OPCODE(ADC, ABX, 4),
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/* 7E */ NEW_OPCODE(ROR, ABX, 7),
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/* 7F */ NEW_OPCODE(XXX, IMP, 0),
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/* 80 */ NEW_OPCODE(XXX, IMP, 0),
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/* 81 */ NEW_OPCODE(STA, INDX, 6),
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/* 82 */ NEW_OPCODE(XXX, IMP, 0),
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/* 83 */ NEW_OPCODE(XXX, IMP, 0),
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/* 84 */ NEW_OPCODE(STY, ZPG, 3),
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/* 85 */ NEW_OPCODE(STA, ZPG, 3),
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/* 86 */ NEW_OPCODE(STX, ZPG, 3),
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/* 87 */ NEW_OPCODE(XXX, IMP, 0),
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/* 88 */ NEW_OPCODE(DEY, IMP, 2),
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/* 89 */ NEW_OPCODE(XXX, IMP, 0),
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/* 8A */ NEW_OPCODE(TXA, IMP, 2),
|
||||
/* 8B */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* 8C */ NEW_OPCODE(STY, ABS, 4),
|
||||
/* 8D */ NEW_OPCODE(STA, ABS, 4),
|
||||
/* 8E */ NEW_OPCODE(STX, ABS, 4),
|
||||
/* 8F */ NEW_OPCODE(XXX, IMP, 0),
|
||||
|
||||
/* 90 */ NEW_OPCODE(BCC, REL, 2),
|
||||
/* 91 */ NEW_OPCODE(STA, INDY, 6),
|
||||
/* 92 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* 93 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* 94 */ NEW_OPCODE(STY, ZPX, 4),
|
||||
/* 95 */ NEW_OPCODE(STA, ZPX, 4),
|
||||
/* 96 */ NEW_OPCODE(STX, ZPY, 4),
|
||||
/* 97 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* 98 */ NEW_OPCODE(TYA, IMP, 2),
|
||||
/* 99 */ NEW_OPCODE(STA, ABY, 5),
|
||||
/* 9A */ NEW_OPCODE(TXS, IMP, 2),
|
||||
/* 9B */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* 9C */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* 9D */ NEW_OPCODE(STA, ABX, 5),
|
||||
/* 9E */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* 9F */ NEW_OPCODE(XXX, IMP, 0),
|
||||
|
||||
/* A0 */ NEW_OPCODE(LDY, IMM, 2),
|
||||
/* A1 */ NEW_OPCODE(LDA, INDX, 6),
|
||||
/* A2 */ NEW_OPCODE(LDX, IMM, 2),
|
||||
/* A3 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* A4 */ NEW_OPCODE(LDY, ZPG, 3),
|
||||
/* A5 */ NEW_OPCODE(LDA, ZPG, 3),
|
||||
/* A6 */ NEW_OPCODE(LDX, ZPG, 3),
|
||||
/* A7 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* A8 */ NEW_OPCODE(TAY, IMP, 2),
|
||||
/* A9 */ NEW_OPCODE(LDA, IMM, 2),
|
||||
/* AA */ NEW_OPCODE(TAX, IMP, 2),
|
||||
/* AB */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* AC */ NEW_OPCODE(LDY, ABS, 4),
|
||||
/* AD */ NEW_OPCODE(LDA, ABS, 4),
|
||||
/* AE */ NEW_OPCODE(LDX, ABS, 4),
|
||||
/* AF */ NEW_OPCODE(XXX, IMP, 0),
|
||||
|
||||
/* B0 */ NEW_OPCODE(BCS, REL, 2),
|
||||
/* B1 */ NEW_OPCODE(LDA, INDY, 5),
|
||||
/* B2 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* B3 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* B4 */ NEW_OPCODE(LDY, ZPX, 4),
|
||||
/* B5 */ NEW_OPCODE(LDA, ZPX, 4),
|
||||
/* B6 */ NEW_OPCODE(LDX, ZPY, 4),
|
||||
/* B7 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* B8 */ NEW_OPCODE(CLV, IMP, 2),
|
||||
/* B9 */ NEW_OPCODE(LDA, ABY, 4),
|
||||
/* BA */ NEW_OPCODE(TSX, IMP, 2),
|
||||
/* BB */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* BC */ NEW_OPCODE(LDY, ABX, 4),
|
||||
/* BD */ NEW_OPCODE(LDA, ABX, 4),
|
||||
/* BE */ NEW_OPCODE(LDX, ABY, 4),
|
||||
/* BF */ NEW_OPCODE(XXX, IMP, 0),
|
||||
|
||||
/* C0 */ NEW_OPCODE(CPY, IMM, 2),
|
||||
/* C1 */ NEW_OPCODE(CMP, INDX, 6),
|
||||
/* C2 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* C3 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* C4 */ NEW_OPCODE(CPY, ZPG, 3),
|
||||
/* C5 */ NEW_OPCODE(CMP, ZPG, 3),
|
||||
/* C6 */ NEW_OPCODE(DEC, ZPG, 5),
|
||||
/* C7 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* C8 */ NEW_OPCODE(INY, IMP, 2),
|
||||
/* C9 */ NEW_OPCODE(CMP, IMM, 2),
|
||||
/* CA */ NEW_OPCODE(DEX, IMP, 2),
|
||||
/* CB */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* CC */ NEW_OPCODE(CPY, ABS, 4),
|
||||
/* CD */ NEW_OPCODE(CMP, ABS, 4),
|
||||
/* CE */ NEW_OPCODE(DEC, ABS, 6),
|
||||
/* CF */ NEW_OPCODE(XXX, IMP, 0),
|
||||
|
||||
/* D0 */ NEW_OPCODE(BNE, REL, 2),
|
||||
/* D1 */ NEW_OPCODE(CMP, INDY, 5),
|
||||
/* D2 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* D3 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* D4 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* D5 */ NEW_OPCODE(CMP, ZPX, 4),
|
||||
/* D6 */ NEW_OPCODE(DEC, ZPX, 6),
|
||||
/* D7 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* D8 */ NEW_OPCODE(CLD, IMP, 2),
|
||||
/* D9 */ NEW_OPCODE(CMP, ABY, 4),
|
||||
/* DA */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* DB */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* DC */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* DD */ NEW_OPCODE(CMP, ABX, 4),
|
||||
/* DE */ NEW_OPCODE(DEC, ABX, 7),
|
||||
/* DF */ NEW_OPCODE(XXX, IMP, 0),
|
||||
|
||||
/* E0 */ NEW_OPCODE(CPX, IMM, 2),
|
||||
/* E1 */ NEW_OPCODE(SBC, INDX, 6),
|
||||
/* E2 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* E3 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* E4 */ NEW_OPCODE(CPX, ZPG, 3),
|
||||
/* E5 */ NEW_OPCODE(SBC, ZPG, 3),
|
||||
/* E6 */ NEW_OPCODE(INC, ZPG, 5),
|
||||
/* E7 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* E8 */ NEW_OPCODE(INX, IMP, 2),
|
||||
/* E9 */ NEW_OPCODE(SBC, IMM, 2),
|
||||
/* EA */ NEW_OPCODE(NOP, IMP, 2),
|
||||
/* EB */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* EC */ NEW_OPCODE(CPX, ABS, 4),
|
||||
/* ED */ NEW_OPCODE(SBC, ABS, 4),
|
||||
/* EE */ NEW_OPCODE(INC, ABS, 6),
|
||||
/* EF */ NEW_OPCODE(XXX, IMP, 0),
|
||||
|
||||
/* F0 */ NEW_OPCODE(BEQ, REL, 2),
|
||||
/* F1 */ NEW_OPCODE(SBC, INDY, 5),
|
||||
/* F2 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* F3 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* F4 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* F5 */ NEW_OPCODE(SBC, ZPX, 4),
|
||||
/* F6 */ NEW_OPCODE(INC, ZPX, 6),
|
||||
/* F7 */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* F8 */ NEW_OPCODE(SED, IMP, 2),
|
||||
/* F9 */ NEW_OPCODE(SBC, ABY, 4),
|
||||
/* FA */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* FB */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* FC */ NEW_OPCODE(XXX, IMP, 0),
|
||||
/* FD */ NEW_OPCODE(SBC, ABX, 4),
|
||||
/* FE */ NEW_OPCODE(INC, ABX, 7),
|
||||
/* FF */ NEW_OPCODE(XXX, IMP, 0)
|
||||
};
|
||||
Loading…
Reference in a new issue