diff --git a/src/addressing.rs b/src/addressing.rs
index 25fda37..24fb736 100644
--- a/src/addressing.rs
+++ b/src/addressing.rs
@@ -24,4 +24,14 @@ impl CPU
 
 		print!("{: <30}", format!("#${:02X}", bus.borrow().read_cpu(self.absolute_addr)));
 	}
+
+	pub fn zpg(&mut self)
+	{
+		let bus = self.bus.upgrade().unwrap();
+
+		self.absolute_addr = bus.borrow().read_cpu(self.pc) as u16;
+		self.pc += 1;
+
+		print!("{: <30}", format!("${:02X} = {:02X}", self.absolute_addr, bus.borrow().read_cpu(self.absolute_addr)))
+	}
 }
\ No newline at end of file
diff --git a/src/bus.rs b/src/bus.rs
index acbb8a2..1947822 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -24,16 +24,6 @@ impl Bus
 		}
 	}
 
-	pub fn run(&self)
-	{
-		let cpu = self.cpu.upgrade().unwrap();
-
-		loop
-		{
-			cpu.borrow_mut().cycle();
-		}
-	}
-
 	pub fn attach_cpu(&mut self, cpu: &Rc<RefCell<CPU>>)
 	{	
 		self.cpu = Rc::downgrade(cpu);
@@ -49,4 +39,15 @@ impl Bus
 			_ => panic!("Tried to access invalid memory address {}", addr)
 		}
 	}
+
+	pub fn write_cpu(&mut self, addr: u16, val: u8) 
+	{
+		match addr 
+		{
+			0..=0x1FFF 		=> self.ram[(addr & 0x7FF) as usize] = val,
+			0x8000..=0xFFFF => self.cartridge.write_prg(addr & 0x7FFF, val),
+
+			_ => panic!("Tried to access invalid memory address {}", addr)
+		}
+	}
 }
\ No newline at end of file
diff --git a/src/cartridge.rs b/src/cartridge.rs
index 8134d24..384f054 100644
--- a/src/cartridge.rs
+++ b/src/cartridge.rs
@@ -52,4 +52,9 @@ impl Cartridge
 	{
 		self.prg[(addr & 0x3FFF) as usize]
 	}
+
+	pub fn write_prg(&mut self, addr: u16, val: u8)
+	{
+		// nothing
+	}
 }
\ No newline at end of file
diff --git a/src/cpu.rs b/src/cpu.rs
index 83a32a6..f9cfe38 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -61,6 +61,7 @@ impl CPU
 		let mut instr_set = [UNDEF_INSTR; 256];
 
 		instr_set[0x4C] = Option::Some(instr!(jmp, abs, 3, 3));
+		instr_set[0x86] = Option::Some(instr!(stx, zpg, 3, 2));
 		instr_set[0xA2] = Option::Some(instr!(ldx, imm, 2, 2));
 
 		CPU {
diff --git a/src/instructions.rs b/src/instructions.rs
index 521baa7..8e8037a 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -1,5 +1,40 @@
 use crate::cpu::CPU;
 
+#[allow(dead_code)]
+enum Bit
+{
+	Negative 	= 7,
+	Overflow 	= 6,
+	Decimal 	= 3,
+	Interrupt 	= 2,
+	Zero		= 1,
+	Carry	 	= 0,
+}
+
+macro_rules! set_flag
+{
+	($target: expr, $flag: expr) => 
+	{
+		$target |= (1u8 << ($flag as u8))
+	}
+}
+
+macro_rules! clear_flag
+{
+	($target: expr, $flag: expr) => 
+	{
+		$target &= !(1u8 << ($flag as u8))
+	}
+}
+
+macro_rules! set_flag_to
+{
+	($target: expr, $flag: expr, $value: expr) => 
+	{
+		$target = ($target & !(1u8 << ($flag as u8))) | (($value as u8) << ($flag as u8));
+	}
+}
+
 impl CPU 
 {
 	fn fetch(&mut self) -> u8
@@ -16,5 +51,15 @@ impl CPU
 	pub fn ldx(&mut self)
 	{
 		self.x = self.fetch();
+
+		set_flag_to!(self.p, Bit::Negative, (self.x & (1u8 << 7)) > 0);
+		set_flag_to!(self.p, Bit::Zero, self.x == 0);
+	}
+
+	pub fn stx(&mut self)
+	{
+		let bus = self.bus.upgrade().unwrap();
+
+		bus.borrow_mut().write_cpu(self.absolute_addr, self.x);
 	}
 }
\ No newline at end of file
diff --git a/src/nes.rs b/src/nes.rs
index 5395cdd..13b92e8 100644
--- a/src/nes.rs
+++ b/src/nes.rs
@@ -29,6 +29,9 @@ impl NES
 	{
 		self.cpu.borrow_mut().powerup();
 
-		self.bus.borrow().run();
+		loop
+		{
+			self.cpu.borrow_mut().cycle();
+		}
 	}
 }
\ No newline at end of file