more isntructions

src/addressing.rs

@@ -1,4 +1,4 @@
-use crate::cpu::CPU;
+use crate::cpu::{CPU, FetchType};
 
 impl CPU
 {
@@ -12,9 +12,18 @@ impl CPU
 		self.pc += 2;
 		self.absolute_addr = (hi << 8) | lo;
 
+		self.fetch_type = FetchType::Mem;
+
 		print!("{: <30}", format!("${:04X}", self.absolute_addr));
 	}
 
+	pub fn acc(&mut self)
+	{
+		self.fetch_type = FetchType::Acc;
+
+		print!("{: <30}", "A");
+	}
+
 	pub fn imm(&mut self)
 	{
 		let bus = self.bus.upgrade().unwrap();
@@ -22,6 +31,8 @@ impl CPU
 		self.absolute_addr = self.pc;
 		self.pc += 1;
 
+		self.fetch_type = FetchType::Mem;
+
 		print!("{: <30}", format!("#${:02X}", bus.borrow().read_cpu(self.absolute_addr)));
 	}
 
@@ -47,6 +58,8 @@ impl CPU
 		self.absolute_addr = bus.borrow().read_cpu(self.pc) as u16;
 		self.pc += 1;
 
+		self.fetch_type = FetchType::Mem;
+
 		print!("{: <30}", format!("${:02X} = {:02X}", self.absolute_addr, bus.borrow().read_cpu(self.absolute_addr)))
 	}
 }

src/cpu.rs

@@ -34,12 +34,20 @@ macro_rules! instr
 	}
 }
 
+pub enum FetchType
+{
+	Acc,
+	Mem
+}
+
 pub struct CPU
 {
 	pub cycle: u8,
 	total_cycles: u64,
+
 	pub absolute_addr: u16,
 	pub relative_addr: i8,
+	pub fetch_type: FetchType,
 
 	pub acc: u8,
 	pub x: u8,
@@ -62,6 +70,7 @@ impl CPU
 
 		instr_set[0x08] = instr!(php, imp, 3, 1);
 		instr_set[0x09] = instr!(ora, imm, 2, 2);
+		instr_set[0x0A] = instr!(asl, acc, 2, 1);
 
 		instr_set[0x10] = instr!(bpl, rel, 2, 2);
 		instr_set[0x18] = instr!(clc, imp, 2, 1);
@@ -70,11 +79,13 @@ impl CPU
 		instr_set[0x24] = instr!(bit, zpg, 3, 2);
 		instr_set[0x28] = instr!(plp, imp, 4, 1);
 		instr_set[0x29] = instr!(and, imm, 2, 2);
+		instr_set[0x2A] = instr!(rol, acc, 2, 1);
 
 		instr_set[0x30] = instr!(bmi, rel, 2, 2);
 		instr_set[0x38] = instr!(sec, imp, 2, 1);
 
 		instr_set[0x40] = instr!(rti, imp, 6, 1);
+		instr_set[0x4A] = instr!(lsr, acc, 2, 1);
 		instr_set[0x48] = instr!(pha, imp, 3, 1);
 		instr_set[0x49] = instr!(eor, imm, 2, 2);
 		instr_set[0x4C] = instr!(jmp, abs, 3, 3);
@@ -84,6 +95,7 @@ impl CPU
 		instr_set[0x60] = instr!(rts, imp, 6, 1);
 		instr_set[0x68] = instr!(pla, imp, 4, 1);
 		instr_set[0x69] = instr!(adc, imm, 2, 2);
+		instr_set[0x6A] = instr!(ror, acc, 2, 1);
 		
 		instr_set[0x70] = instr!(bvs, rel, 2, 2);
 		instr_set[0x78] = instr!(sei, imp, 2, 1);
@@ -93,6 +105,7 @@ impl CPU
 		instr_set[0x86] = instr!(stx, zpg, 3, 2);
 		instr_set[0x88] = instr!(dey, imp, 2, 1);
 		instr_set[0x8A] = instr!(txa, imp, 2, 1);
+		instr_set[0x8D] = instr!(sta, abs, 4, 3);
 		instr_set[0x8E] = instr!(stx, abs, 4, 3);
 
 		instr_set[0x90] = instr!(bcc, rel, 2, 2);
@@ -101,6 +114,7 @@ impl CPU
 
 		instr_set[0xA0] = instr!(ldy, imm, 2, 2);
 		instr_set[0xA2] = instr!(ldx, imm, 2, 2);
+		instr_set[0xA5] = instr!(lda, zpg, 3, 2);
 		instr_set[0xA8] = instr!(tay, imp, 2, 1);
 		instr_set[0xA9] = instr!(lda, imm, 2, 2);
 		instr_set[0xAA] = instr!(tax, imp, 2, 1);
@@ -130,8 +144,10 @@ impl CPU
 		CPU {
 			cycle: 0,
 			total_cycles: 0,
+
 			absolute_addr: 0,
 			relative_addr: 0,
+			fetch_type: FetchType::Mem,
 
 			acc: 0,
 			x: 0,

src/instructions.rs

@@ -1,4 +1,4 @@
-use crate::cpu::CPU;
+use crate::cpu::{CPU, FetchType};
 use crate::bus::Bus;
 use std::cell::Ref;
 
@@ -206,12 +206,74 @@ macro_rules! cmp_fn
 	}
 }
 
+macro_rules! bit_shift_carry
+{
+	($val: ident, <<) => { ($val & 0x80) == 0x80 };
+	($val: ident, >>) => { ($val & 0x01) == 0x01 };
+}
+
+macro_rules! handle_carry
+{
+	($val: ident, $carry: ident, <<) => { $val |= ($carry as u8); };
+	($val: ident, $carry: ident, >>) => { $val |= (($carry as u8) << 7); };
+}
+
+macro_rules! bit_shift_fn 
+{
+	($name: ident, $direction: tt, $rotate: literal) =>
+	{
+		pub fn $name(&mut self)
+		{
+			let mut val = self.fetch();
+
+			let carry = test_flag!(self.p, Bit::Carry);
+			set_flag_to!(self.p, Bit::Carry, bit_shift_carry!(val, $direction));
+
+			val = val $direction 1;
+			match $rotate
+			{
+				false => { },
+				true  => { handle_carry!(val, carry, $direction); }
+			};
+	
+			set_flag_to!(self.p, Bit::Zero, val == 0x00);
+			set_flag_to!(self.p, Bit::Negative, (val & 0x80) == 0x80);
+	
+			self.ditch(val);
+		}
+	}
+}
+
 impl CPU 
 {
 	fn fetch(&mut self) -> u8
 	{
-		let bus = self.bus.upgrade().unwrap();
+		match self.fetch_type
-		return bus.borrow().read_cpu(self.absolute_addr);
+		{
+			FetchType::Mem => {
+				let bus = self.bus.upgrade().unwrap();
+				return bus.borrow().read_cpu(self.absolute_addr);
+			},
+
+			FetchType::Acc => {
+				self.acc
+			}
+		}
+	}
+
+	fn ditch(&mut self, value: u8)
+	{
+		match self.fetch_type
+		{
+			FetchType::Mem => {
+				let bus = self.bus.upgrade().unwrap();
+				bus.borrow_mut().write_cpu(self.absolute_addr, value);
+			},
+
+			FetchType::Acc => {
+				self.acc = value;
+			}
+		}
 	}
 
 	branch_on_fn!(bcc, Bit::Carry, 		false);
@@ -258,6 +320,11 @@ impl CPU
 	inc_dec_fn!(dex, x, false);
 	inc_dec_fn!(dey, y, false);
 
+	bit_shift_fn!(asl, <<, false);
+	bit_shift_fn!(lsr, >>, false);
+	bit_shift_fn!(rol, <<, true);
+	bit_shift_fn!(ror, >>, true);
+
 
 	pub fn adc(&mut self)
 	{