improved debug log formatting

Cargo.lock

@@ -2,6 +2,15 @@
 # It is not intended for manual editing.
 version = 3
 
+[[package]]
+name = "copystr"
+version = "0.0.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "547ed93b8f3c851afaaf05fe51e49c31a735c098e9fd8d3fbcf572262bdc0d43"
+
 [[package]]
 name = "rusty-nes"
 version = "0.1.0"
+dependencies = [
+ "copystr",
+]

Cargo.toml

@@ -6,3 +6,4 @@ edition = "2021"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
+copystr = "0.0.5"

src/addressing.rs

@@ -0,0 +1,27 @@
+use crate::cpu::CPU;
+
+impl CPU
+{
+	pub fn abs(&mut self)
+	{
+		let bus = self.bus.upgrade().unwrap();
+
+		let lo = bus.borrow().read_cpu(self.pc) as u16;
+		let hi = bus.borrow().read_cpu(self.pc + 1) as u16;
+
+		self.pc += 2;
+		self.absolute_addr = (hi << 8) | lo;
+
+		print!("{: <30}", format!("${:04X}", self.absolute_addr));
+	}
+
+	pub fn imm(&mut self)
+	{
+		let bus = self.bus.upgrade().unwrap();
+
+		self.absolute_addr = self.pc;
+		self.pc += 1;
+
+		print!("{: <30}", format!("#${:02X}", bus.borrow().read_cpu(self.absolute_addr)));
+	}
+}

src/bus.rs

@@ -30,7 +30,7 @@ impl Bus
 
 		loop
 		{
-			cpu.borrow_mut().execute();
+			cpu.borrow_mut().cycle();
 		}
 	}
 

src/cartridge.rs

@@ -1,4 +1,4 @@
-use std::{fs::{self, File}, io::{BufReader, Read}};
+use std::{fs::File, io::{BufReader, Read}};
 
 struct Header 
 {
@@ -6,6 +6,7 @@ struct Header
 	chr_blocks: u8
 }
 
+#[allow(dead_code)]
 pub struct Cartridge
 {
 	header: Header,

src/cpu.rs

@@ -1,26 +1,74 @@
 use std::cell::RefCell;
 use std::rc::{Rc, Weak};
+use copystr::s3;
 
 use crate::bus::Bus;
 
+type InstrFn = fn(&mut CPU);
+type AddrFn = fn(&mut CPU);
+
+#[derive(Clone, Copy)]
+struct Instruction
+{
+	action: InstrFn,
+	addressing: AddrFn,
+	cycles: u8,
+	length: u8,
+
+	name: s3
+}
+
+macro_rules! instr 
+{
+	($instr: ident, $addr: ident, $cyc: literal, $len: literal) =>
+	{
+		Instruction 
+		{
+			action: CPU::$instr,
+			addressing: CPU::$addr,
+			cycles: $cyc,
+			length: $len,
+
+			name: s3::new(stringify!($instr)).unwrap()
+		}
+	}
+}
+
 pub struct CPU
 {
-	acc: u8,
+	pub cycle: u8,
-	x: u8,
+	total_cycles: u64,
-	y: u8,
+	pub absolute_addr: u16,
-	p: u8,
+	pub relative_addr: u8,
-	sp: u8,
 
-	pc: u16,
+	pub acc: u8,
+	pub x: u8,
+	pub y: u8,
+	pub p: u8,
+	pub sp: u8,
+	pub pc: u16,
 
-	bus: Weak<RefCell<Bus>>
+	pub bus: Weak<RefCell<Bus>>,
+
+	instruction_set: [Option<Instruction>; 256]
 }
 
 impl CPU 
 {
 	pub fn new(bus: &Rc<RefCell<Bus>>) -> CPU 
 	{
+		const UNDEF_INSTR: Option<Instruction> = None;
+		let mut instr_set = [UNDEF_INSTR; 256];
+
+		instr_set[0x4C] = Option::Some(instr!(jmp, abs, 3, 3));
+		instr_set[0xA2] = Option::Some(instr!(ldx, imm, 2, 2));
+
 		CPU {
+			cycle: 0,
+			total_cycles: 0,
+			absolute_addr: 0,
+			relative_addr: 0,
+
 			acc: 0,
 			x: 0,
 			y: 0,
@@ -29,7 +77,9 @@ impl CPU
 
 			pc: 0,
 
-			bus: Rc::downgrade(bus)
+			bus: Rc::downgrade(bus),
+
+			instruction_set: instr_set
 		}
 	}
 
@@ -42,19 +92,54 @@ impl CPU
 		self.y = 0;
 		self.sp = 0xFD;
 
+		self.total_cycles = 0;
+		self.cycle = 6;
+
 		// TODO: This is just for the nestest.nes
 		self.pc = 0xC000;
 	}
 
-	pub fn execute(&mut self)
+	pub fn cycle(&mut self)
+	{
+		self.total_cycles += 1;
+
+		if self.cycle > 0
+		{
+			self.cycle -= 1;
+			return;
+		}
+
+		self.execute();
+	}
+
+	fn execute(&mut self)
 	{
 		let bus = self.bus.upgrade().unwrap();
 		let opcode: u8 = bus.borrow().read_cpu(self.pc);
+		let instr = self.instruction_set[opcode as usize].expect(&format!("Unimplemented opcode {:02X}", opcode));
+
+		print!("{:04X}  ", self.pc);
+		for byte in 0..3
+		{
+			if byte < instr.length 
+			{
+				print!("{:02X} ", bus.borrow().read_cpu(self.pc + byte as u16));
+			}
+			else
+			{
+				print!("   ");	
+			}
+		}
+
+		print!(" {} ", instr.name.to_string().to_uppercase());
+
 		self.pc += 1;
 
-		match (opcode)
+		(instr.addressing)(self);
-		{
+		(instr.action)(self);
-			_ => panic!("Unimplemented opcode {:X}", opcode)
+
-		}
+		self.cycle += instr.cycles;
+
+		println!("A:{:02X} X:{:02X} Y:{:02X} P:{:02X} SP:{:02X} CYC:{}", self.acc, self.x, self.y, self.p, self.sp, self.total_cycles);
 	}
 }

src/instructions.rs

@@ -0,0 +1,20 @@
+use crate::cpu::CPU;
+
+impl CPU 
+{
+	fn fetch(&mut self) -> u8
+	{
+		let bus = self.bus.upgrade().unwrap();
+		return bus.borrow().read_cpu(self.absolute_addr);
+	}
+
+	pub fn jmp(&mut self)
+	{
+		self.pc = self.absolute_addr;
+	}
+
+	pub fn ldx(&mut self)
+	{
+		self.x = self.fetch();
+	}
+}

src/main.rs

@@ -1,6 +1,8 @@
 mod nes;
 mod bus;
 mod cpu;
+mod instructions;
+mod addressing;
 mod cartridge;
 
 use nes::NES;