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mcp23s17 ansprechbar

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This commit is contained in:
Tristan Krause 2019-03-25 13:42:32 +01:00
parent 08795e7547
commit d3afcc2f37
7 changed files with 114 additions and 46 deletions
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B15F.elf
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52
B15F.hex
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@ -6,19 +6,45 @@
:100050000C9464000C9464000C9464000C94640090 :100050000C9464000C9464000C9464000C94640090
:100060000C9464000C9464000C9464000C94640080 :100060000C9464000C9464000C9464000C94640080
:100070000C9464000C9464000C9464000C94640070 :100070000C9464000C9464000C9464000C94640070
:100080000C9464000C9464000C9464009F00112490 :100080000C9464000C9464000C94640070011124BE
:100090001FBECFEFD0E4DEBFCDBF21E0A0E0B1E0D6 :100090001FBECFEFD0E4DEBFCDBF21E0A0E0B1E0D6
:1000A00001C01D92A430B207E1F710E0C7E4D0E030 :1000A00001C01D92A430B207E1F710E0C7E4D0E030
:1000B00004C02197FE010E94AA00C634D107C9F7E7 :1000B00004C02197FE010E947B01C634D107C9F715
:1000C0000E9495000C94B3000C9400000895259AAA :1000C0000E9458010C9484010C9400000895249A15
:1000D0002698279A529A539A549A80EB84B980E5CD :1000D000259A2698279A529A539A549A80E58CBD6D
:1000E0008CBD81E08DBD08955A985B985C9860FD49 :1000E00081E08DBD5A985B985C985A9A5B9A5C9AAD
:1000F0005A9A61FD5B9A62FD5C9A08956EBD0DB4DB :1000F00008955A985B985C9860FD5A9A61FD5B9AE6
:1001000007FEFDCF87E893E10197F1F700C00000FB :1001000062FD5C9A08956EBD0DB407FEFDCF8EB5FD
:100110008EB50895FC01718360834283089560E485 :100110000895FC0171836083428308951F93CF93F8
:10012000FC01808191810C947E0083E091E00E942B :10012000DF93EC01162F6A81888199810E94790002
:10013000670088E08EBD0DB407FEFDCFFBCF83E0E6 :1001300060E4888199810E94830060E088819981D0
:1001400091E00E94660042E063E071E080E091E0AF :100140000E948300612F888199810E94830067E06B
:100150000C948A00EE0FFF1F0024001C0BBE0790BA :1001500088819981DF91CF911F910C9479001F9331
:0A016000F691E02D0994F894FFCF0A :10016000CF93DF93EC01162F6A81888199810E94D9
:10017000790060E4888199810E94830061E0888130
:1001800099810E948300612F888199810E94830058
:1001900067E088819981DF91CF911F910C9479005C
:1001A0001F93CF93DF93EC01162F6A818881998189
:1001B0000E94790060E4888199810E94830062E155
:1001C000888199810E948300612F888199810E9492
:1001D000830067E088819981DF91CF911F910C9412
:1001E00079001F93CF93DF93EC01162F6A818881EA
:1001F00099810E94790060E4888199810E9483003E
:1002000063E1888199810E948300612F88819981AF
:100210000E94830067E088819981DF91CF911F91CF
:100220000C9479001F93CF93DF93EC016A8188814E
:1002300099810E94790061E4888199810E948300FC
:1002400062E1888199810E94830060E088819981C0
:100250000E948300182F67E0888199810E947900AD
:10026000812FDF91CF911F9108951F93CF93DF933B
:10027000EC016A81888199810E94790061E488811A
:1002800099810E94830063E1888199810E948300A3
:1002900060E0888199810E948300182F67E088813F
:1002A00099810E947900812FDF91CF911F9108954C
:1002B00083E091E00E94670060E080E091E00E94AE
:1002C0008E006FEF80E091E00E94AF0080E091E04F
:1002D0000E943501682F80E091E00E94D000F6CFA7
:1002E00083E091E00E94660042E063E071E080E01C
:1002F00091E00C948900EE0FFF1F0024001C0BBE40
:0C0300000790F691E02D0994F894FFCFCF
:00000001FF :00000001FF

7
main.cpp
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@ -9,12 +9,11 @@ MCP23S17 beba0(spi, SPIADR::BEBA0);
int main() { int main() {
spi.init(); spi.init();
beba0.setDirA(0x00); // alle Ausgang
beba0.setDirB(0xFF); // alle Eingang
while(1) { while(1) {
beba0.writePortA(beba0.readPortB());
SPDR = 8;
while(!(SPSR & _BV(SPIF)));
//spi.pushByte(8);
} }
return 0; return 0;

77
mcp23s17.cpp
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@ -2,33 +2,60 @@
MCP23S17::MCP23S17(SPI& spi, uint8_t adr) : spi(spi), adr(adr) MCP23S17::MCP23S17(SPI& spi, uint8_t adr) : spi(spi), adr(adr)
{ {
} }
void MCP23S17::setDirA(uint8_t dir) const
void MCP23S17::setPort(uint8_t port) const
{ {
spi.pushByte(0x40);
/*
spi.setAdr(0);
_delay_ms(1);
spi.setAdr(adr); spi.setAdr(adr);
spi.pushByte(0x40); // spi.pushByte(MCP23S17_OPCODE | MCP23S17_WRITE);
spi.pushByte(0x00); // DIR A spi.pushByte(MCP23S17_DIRA);
spi.pushByte(0x00); // alle ausgang spi.pushByte(dir);
spi.setAdr(SPIADR::NONE);
spi.setAdr(0); }
_delay_ms(1);
spi.setAdr(adr); void MCP23S17::setDirB(uint8_t dir) const
spi.pushByte(0x40); {
spi.pushByte(0x12); spi.setAdr(adr);
spi.pushByte(0xF0); spi.pushByte(MCP23S17_OPCODE | MCP23S17_WRITE);
spi.setAdr(0); spi.pushByte(MCP23S17_DIRB);
spi.pushByte(dir);
/*while(1) { spi.setAdr(SPIADR::NONE);
PORTB ^= _BV(PB7); }
_delay_ms(1);
}*/ void MCP23S17::writePortA(uint8_t port) const
{
spi.setAdr(adr);
spi.pushByte(MCP23S17_OPCODE | MCP23S17_WRITE);
spi.pushByte(MCP23S17_PORTA);
spi.pushByte(port);
spi.setAdr(SPIADR::NONE);
}
void MCP23S17::writePortB(uint8_t port) const
{
spi.setAdr(adr);
spi.pushByte(MCP23S17_OPCODE | MCP23S17_WRITE);
spi.pushByte(MCP23S17_PORTB);
spi.pushByte(port);
spi.setAdr(SPIADR::NONE);
}
uint8_t MCP23S17::readPortA(void) const
{
spi.setAdr(adr);
spi.pushByte(MCP23S17_OPCODE | MCP23S17_READ);
spi.pushByte(MCP23S17_PORTA);
uint8_t port = spi.pushByte(0);
spi.setAdr(SPIADR::NONE);
return port;
}
uint8_t MCP23S17::readPortB(void) const
{
spi.setAdr(adr);
spi.pushByte(MCP23S17_OPCODE | MCP23S17_READ);
spi.pushByte(MCP23S17_PORTB);
uint8_t port = spi.pushByte(0);
spi.setAdr(SPIADR::NONE);
return port;
} }

15
mcp23s17.h
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@ -3,11 +3,24 @@
#include "spi.h" #include "spi.h"
constexpr uint8_t MCP23S17_DIRA = 0x00;
constexpr uint8_t MCP23S17_DIRB = 0x01;
constexpr uint8_t MCP23S17_PORTA = 0x12;
constexpr uint8_t MCP23S17_PORTB = 0x13;
constexpr uint8_t MCP23S17_READ = 0x01;
constexpr uint8_t MCP23S17_WRITE = 0x00;
constexpr uint8_t MCP23S17_OPCODE = 0x40;
class MCP23S17 class MCP23S17
{ {
public: public:
MCP23S17(SPI&, uint8_t); MCP23S17(SPI&, uint8_t);
void setPort(uint8_t) const; void setDirA(uint8_t dir) const;
void setDirB(uint8_t dir) const;
void writePortA(uint8_t) const;
void writePortB(uint8_t) const;
uint8_t readPortA(void) const;
uint8_t readPortB(void) const;
private: private:
SPI& spi; SPI& spi;

7
spi.cpp
View file

@ -8,22 +8,24 @@ void SPI::init(void) const
{ {
// Konfiguriere SPI DDRs // Konfiguriere SPI DDRs
dMode(SLSL, OUT);
dMode(MOSI, OUT); dMode(MOSI, OUT);
dMode(MISO, IN); dMode(MISO, IN);
dMode(SCLK, OUT); dMode(SCLK, OUT);
// Konfiguriere DMUX DDRs // Konfiguriere DMUX DDRs
dMode(DMUX1, OUT); dMode(DMUX1, OUT);
dMode(DMUX2, OUT); dMode(DMUX2, OUT);
dMode(DMUX3, OUT); dMode(DMUX3, OUT);
DDRB = 0xB0;
// aktiviere SPI, Master Modus, SPI Modus 0 // aktiviere SPI, Master Modus, SPI Modus 0
// F_SPI = F_CPU / 2 (prescaler 2) // F_SPI = F_CPU / 2 (prescaler 2)
SPCR = _BV(SPE) | _BV(MSTR); SPCR = _BV(SPE) | _BV(MSTR);
SPSR = _BV(SPI2X); SPSR = _BV(SPI2X);
// waehle keinen SPI Slave aus
setAdr(SPIADR::NONE);
} }
/*void SPI::setFreq(uint32_t freq) const /*void SPI::setFreq(uint32_t freq) const
@ -49,6 +51,5 @@ uint8_t SPI::pushByte(uint8_t b) const
{ {
SPDR = b; SPDR = b;
while(!(SPSR & _BV(SPIF))); while(!(SPSR & _BV(SPIF)));
_delay_ms(1);
return SPDR; return SPDR;
} }

2
spi.h
View file

@ -5,6 +5,7 @@
#include <stdint.h> #include <stdint.h>
#include "pio.h" #include "pio.h"
#define SLSL B4
#define MOSI B5 #define MOSI B5
#define MISO B6 #define MISO B6
#define SCLK B7 #define SCLK B7
@ -16,6 +17,7 @@
enum SPIADR { enum SPIADR {
BEBA0 = 2, BEBA0 = 2,
BEBA1 = 3, BEBA1 = 3,
NONE = 7,
}; };
class SPI class SPI