fixed ppu postfetching

.gitignore

@@ -5,4 +5,6 @@ out/
 *.json
 
 *.nes
-!roms/nestest.nes
+!roms/nestest.nes
+!roms/cpu_dummy_reads.nes
+!roms/all_instrs.nes

src/Bus.cpp

@@ -204,6 +204,9 @@ void Bus::WritePPU(Word addr, Byte val)
 		if(cartridge.MapCIRAM(addr))
 			cartridge.WriteVRAM(addr, val);
 
+		if (val != 0x00)
+			volatile int jfkd = 3;
+
 		VRAM[addr & 0xFFF] = val;
 	}
 	else if (0x3F00 <= addr && addr < 0x4000)

src/CMakeLists.txt

@@ -13,7 +13,7 @@ add_executable(nesemu
 	"debugger/PPUWatcher.cpp" 
 	"debugger/Disassembler.cpp" 
 	"debugger/MemoryViewer.cpp" 
-	"debugger/NametableViewer.cpp"  "ControllerPort.cpp" "controllers/StandardController.cpp" "gfx/Input.cpp" "debugger/ControllerPortViewer.cpp" "gfx/Screen.cpp" "debugger/Palettes.cpp" "APU.cpp" "debugger/PatternTableViewer.cpp")
+	"debugger/NametableViewer.cpp"  "ControllerPort.cpp" "controllers/StandardController.cpp" "gfx/Input.cpp" "debugger/ControllerPortViewer.cpp" "gfx/Screen.cpp" "debugger/Palettes.cpp" "APU.cpp" "debugger/PatternTableViewer.cpp" "mappers/Mapper003.cpp" "mappers/Mapper001.cpp")
 
 target_include_directories(nesemu PRIVATE
 	mappers

src/CPU.cpp

@@ -87,6 +87,7 @@ void CPU::CreateInstructionTable()
 	InstructionTable[0x08] = NEW_INSTRUCTION(PHP, IMP, 1, 3);
 	InstructionTable[0x09] = NEW_INSTRUCTION(ORA, IMM, 2, 2);
 	InstructionTable[0x0A] = NEW_INSTRUCTION(ASL, ACC, 1, 2);
+	InstructionTable[0x0B] = NEW_ILLGL_INSTR(ANC, IMM, 2, 2);
 	InstructionTable[0x0D] = NEW_INSTRUCTION(ORA, ABS, 3, 4);
 	InstructionTable[0x0C] = NEW_ILLGL_INSTR(NOP, ABS, 3, 4);
 	InstructionTable[0x0E] = NEW_INSTRUCTION(ASL, ABS, 3, 6);
@@ -119,6 +120,7 @@ void CPU::CreateInstructionTable()
 	InstructionTable[0x28] = NEW_INSTRUCTION(PLP, IMP, 1, 4);
 	InstructionTable[0x29] = NEW_INSTRUCTION(AND, IMM, 2, 2);
 	InstructionTable[0x2A] = NEW_INSTRUCTION(ROL, ACC, 1, 2);
+	InstructionTable[0x2B] = NEW_ILLGL_INSTR(ANC, IMM, 2, 2);
 	InstructionTable[0x2C] = NEW_INSTRUCTION(BIT, ABS, 3, 4);
 	InstructionTable[0x2D] = NEW_INSTRUCTION(AND, ABS, 3, 4);
 	InstructionTable[0x2E] = NEW_INSTRUCTION(ROL, ABS, 3, 6);
@@ -163,6 +165,7 @@ void CPU::CreateInstructionTable()
 	InstructionTable[0x55] = NEW_INSTRUCTION(EOR, ZPX, 2, 4);
 	InstructionTable[0x56] = NEW_INSTRUCTION(LSR, ZPX, 2, 6);
 	InstructionTable[0x57] = NEW_ILLGL_INSTR(SRE, ZPX, 2, 6);
+	InstructionTable[0x58] = NEW_INSTRUCTION(CLI, IMP, 1, 2);
 	InstructionTable[0x59] = NEW_INSTRUCTION(EOR, ABY, 3, 4);
 	InstructionTable[0x5A] = NEW_ILLGL_INSTR(NOP, IMP, 1, 2);
 	InstructionTable[0x5B] = NEW_ILLGL_INSTR(SRE, ABY, 3, 7);
@@ -181,6 +184,7 @@ void CPU::CreateInstructionTable()
 	InstructionTable[0x68] = NEW_INSTRUCTION(PLA, IMP, 1, 4);
 	InstructionTable[0x69] = NEW_INSTRUCTION(ADC, IMM, 2, 2);
 	InstructionTable[0x6A] = NEW_INSTRUCTION(ROR, ACC, 1, 2);
+	InstructionTable[0x6B] = NEW_ILLGL_INSTR(ARR, IMM, 2, 2);
 	InstructionTable[0x6C] = NEW_INSTRUCTION(JMP, IND, 3, 5);
 	InstructionTable[0x6D] = NEW_INSTRUCTION(ADC, ABS, 3, 4);
 	InstructionTable[0x6E] = NEW_INSTRUCTION(ROR, ABS, 3, 6);
@@ -228,7 +232,9 @@ void CPU::CreateInstructionTable()
 	InstructionTable[0x98] = NEW_INSTRUCTION(TYA, IMP, 1, 2);
 	InstructionTable[0x99] = NEW_INSTRUCTION(STA, ABY, 3, 5);
 	InstructionTable[0x9A] = NEW_INSTRUCTION(TXS, IMP, 1, 2);
+	InstructionTable[0x9C] = NEW_ILLGL_INSTR(SHY, ABX, 3, 5);
 	InstructionTable[0x9D] = NEW_INSTRUCTION(STA, ABX, 3, 5);
+	InstructionTable[0x9E] = NEW_ILLGL_INSTR(SHX, ABY, 3, 5);
 
 	InstructionTable[0xA0] = NEW_INSTRUCTION(LDY, IMM, 2, 2);
 	InstructionTable[0xA1] = NEW_INSTRUCTION(LDA, IDX, 2, 6);
@@ -273,6 +279,7 @@ void CPU::CreateInstructionTable()
 	InstructionTable[0xC8] = NEW_INSTRUCTION(INY, IMP, 1, 2);
 	InstructionTable[0xC9] = NEW_INSTRUCTION(CMP, IMM, 2, 2);
 	InstructionTable[0xCA] = NEW_INSTRUCTION(DEX, IMP, 1, 2);
+	InstructionTable[0xCB] = NEW_ILLGL_INSTR(SBX, IMM, 2, 2);
 	InstructionTable[0xCC] = NEW_INSTRUCTION(CPY, ABS, 3, 4);
 	InstructionTable[0xCD] = NEW_INSTRUCTION(CMP, ABS, 3, 4);
 	InstructionTable[0xCE] = NEW_INSTRUCTION(DEC, ABS, 3, 6);
@@ -330,7 +337,7 @@ void CPU::CreateInstructionTable()
 
 void CPU::Powerup()
 {
-	status.Raw = 0x34;
+	status.Raw = 0x24;
 	acc = 0;
 	idx = 0;
 	idy = 0;
@@ -362,7 +369,7 @@ void CPU::IRQ()
 
 	Push(pc.Bytes.hi);
 	Push(pc.Bytes.lo);
-	Push(status.Raw | (0x20 << 4));
+	Push(status.Raw | (0x1 << 5));
 
 	status.Flag.InterruptDisable = 1;
 	pc.Bytes.lo = Read(0xFFFE);
@@ -373,7 +380,7 @@ void CPU::NMI()
 {
 	Push(pc.Bytes.hi);
 	Push(pc.Bytes.lo);
-	Push(status.Raw | (0x20 << 4));
+	Push(status.Raw | (0x1 << 5));
 
 	status.Flag.InterruptDisable = 1;
 	pc.Bytes.lo = Read(0xFFFA);
@@ -515,6 +522,16 @@ void CPU::ALR()
 	additionalCycles = 0;
 }
 
+void CPU::ANC()
+{
+	FetchValue();
+	acc &= fetchedVal;
+
+	CHECK_NEGATIVE(acc);
+	CHECK_ZERO(acc);
+	status.Flag.Carry = ((acc & 0x80) == 0x80);
+}
+
 void CPU::AND()
 {
 	FetchValue();
@@ -537,6 +554,20 @@ void CPU::ANE()
 	additionalCycles = 0;
 }
 
+void CPU::ARR()
+{
+	FetchValue();
+	acc &= fetchedVal;
+
+	acc >>= 1;
+	acc |= (status.Flag.Carry << 7);
+
+	CHECK_NEGATIVE(acc);
+	CHECK_ZERO(acc);
+	status.Flag.Overflow = ((acc >> 6) & 0x1) ^ ((acc >> 5) & 0x1);
+	status.Flag.Carry = ((acc >> 6) & 0x1);
+}
+
 void CPU::ASL()
 {
 	FetchValue();
@@ -650,7 +681,7 @@ void CPU::BRK()
 	pc.Raw++;
 	Push(pc.Bytes.hi);
 	Push(pc.Bytes.lo);
-	Push(status.Raw | (0x30 << 4));
+	Push(status.Raw | (0x3 << 4));
 
 	status.Flag.InterruptDisable = 1;
 	pc.Bytes.lo = Read(0xFFFE);
@@ -894,12 +925,11 @@ void CPU::LSR()
 void CPU::LXA()
 {
 	FetchValue();
-	Byte result = (acc & 0xFF) & fetchedVal;
-	acc = result;
-	idx = result;
+	acc = fetchedVal;
+	idx = acc;
 
-	CHECK_NEGATIVE(result);
-	CHECK_ZERO(result);
+	CHECK_NEGATIVE(acc);
+	CHECK_ZERO(acc);
 
 	additionalCycles = 0;
 }
@@ -925,7 +955,7 @@ void CPU::PHA()
 
 void CPU::PHP()
 {
-	Push(status.Raw | (0x30 << 4));
+	Push(status.Raw | (0x3 << 4));
 }
 
 void CPU::PLA()
@@ -1042,6 +1072,18 @@ void CPU::SAX()
 	Write(absoluteAddress.Raw, acc & idx);
 }
 
+void CPU::SBX()
+{
+	FetchValue();
+	Word result = (acc & idx) - fetchedVal;
+
+	CHECK_NEGATIVE(result);
+	CHECK_ZERO(result);
+	status.Flag.Carry = ((acc & idx) >= fetchedVal);
+
+	idx = result;
+}
+
 void CPU::SBC()
 {
 	FetchValue();
@@ -1070,6 +1112,24 @@ void CPU::SEI()
 	status.Flag.InterruptDisable = 1;
 }
 
+void CPU::SHX()
+{
+	Byte result = idx & (rawAddress.Bytes.hi + 1);
+	absoluteAddress.Bytes.hi = result;
+	Write(absoluteAddress.Raw, result);
+
+	additionalCycles = 0;
+}
+
+void CPU::SHY()
+{
+	Byte result = idy & (rawAddress.Bytes.hi + 1);
+	absoluteAddress.Bytes.hi = result;
+	Write(absoluteAddress.Raw, result);
+
+	additionalCycles = 0;
+}
+
 void CPU::SLO()
 {
 	FetchValue();

src/CPU.hpp

@@ -116,12 +116,20 @@ private:
 	/**
 	 * @brief Push a byte to the stack
 	 */
-	inline void Push(Byte val) { Write(0x0100 | (sp--), val); }
+	inline void Push(Byte val) 
+	{ 
+		Write(0x0100 | sp, val); 
+		sp--; 
+	}
 
 	/**
 	 * @brief Pop a byte from the stack.
 	 */
-	inline Byte Pop() { return Read(0x0100 | (++sp)); }
+	inline Byte Pop() 
+	{ 
+		sp++;  
+		return Read(0x0100 | sp); 
+	}
 
 
 	/**
@@ -166,8 +174,10 @@ private:	// Stuff regarding instructions
 	// They simply perform the operations needed
 	void ADC();
 	void ALR();
+	void ANC();
 	void AND();
 	void ANE();
+	void ARR();
 	void ASL();
 	void BCC();
 	void BCS();
@@ -216,10 +226,13 @@ private:	// Stuff regarding instructions
 	void RTI();
 	void RTS();
 	void SAX();
+	void SBX();
 	void SBC();
 	void SEC();
 	void SED();
 	void SEI();
+	void SHX();
+	void SHY();
 	void SLO();
 	void SRE();
 	void STA();
@@ -237,7 +250,7 @@ private:	// CPU internals
 	Byte acc;
 	Byte idx, idy;
 	Address pc;
-	Word sp;
+	Byte sp;
 	StatusFlag status;
 
 	Instruction* currentInstruction = nullptr;

src/Cartridge.cpp

@@ -6,6 +6,8 @@
 
 #include "Mapper.hpp"
 #include "mappers/Mapper000.hpp"
+#include "mappers/Mapper001.hpp"
+#include "mappers/Mapper003.hpp"
 
 Cartridge::Cartridge(Bus* bus) :
 	bus(bus), mapper(nullptr)
@@ -35,6 +37,8 @@ void Cartridge::Load(std::string path)
 	switch (mapperNumber)
 	{
 	case 0:	mapper = new Mapper000(header, file);	break;
+	case 1:	mapper = new Mapper001(header, file);	break;
+	case 3:	mapper = new Mapper003(header, file);	break;
 
 	default:
 		throw std::runtime_error("Unsupported mapper ID " + std::to_string(mapperNumber));

src/Mapper.hpp

@@ -1,6 +1,7 @@
 #pragma once
 
 #include <vector>
+#include "../Log.hpp"
 #include "Types.hpp"
 
 class Mapper
@@ -20,7 +21,7 @@ public:
 	 * enforce nametable mirroring, or even completely remap the address
 	 * to internal VRAM
 	 */
-	bool MapCIRAM(Word& addr)
+	virtual bool MapCIRAM(Word& addr)
 	{
 		if (header.Flag6.IgnoreMirroringBit)
 			return true;
@@ -42,10 +43,14 @@ public:
 	virtual void WriteVRAM(Word addr, Byte val) {}
 
 protected:
-	Mapper(const Header& header) : header(header) {}
+	Mapper(const Header& header) : header(header), prgBanks(header.PrgROM), chrBanks(header.ChrROM)
+	{
+	}
 
 protected:
 	std::vector<Byte> PRG_ROM;
 	std::vector<Byte> CHR_ROM;
+	Byte prgBanks = 0;
+	Byte chrBanks = 0;
 	Header header;
 };

src/PPU.cpp

@@ -157,7 +157,7 @@ void PPU::Tick()
 			current.NametableSel |= temporary.NametableSel & 0x1;
 		}
 
-		if (scanlineType == ScanlineType::PreRender && x >= 280 && x <= 304)
+		if (scanlineType == ScanlineType::PreRender && ppumask.Flag.ShowBackground && x >= 280 && x <= 304)
 		{
 			current.FineY = temporary.FineY;
 			current.CoarseY = temporary.CoarseY;
@@ -180,10 +180,9 @@ void PPU::Tick()
 			palette = 0x00;
 
 		uint8_t colorVal = Read(0x3F00 | (palette << 2) | color);
-		if (colorVal != 0x0f)
-			volatile int dfjk = 3;
-
-		screen->SetPixel(x, y, colorTable[colorVal]);
+		
+		if(ppumask.Flag.ShowBackground)
+			screen->SetPixel(x, y, colorTable[colorVal]);
 	}
 
 	if (cycleType == CycleType::Fetching || cycleType == CycleType::PreFetching)
@@ -197,21 +196,23 @@ void PPU::Tick()
 
 Byte PPU::ReadRegister(Byte id)
 {
+	Byte data = 0;
+
 	// Reading from a register fills the latch with the contents of the register
 	// Write-only regs don't fill the latch
 	// But in any case, the latch contents are returned
 	switch (id)
 	{
 	case 0:
-		latch = ppuctrl.Raw;
+		data = ppuctrl.Raw;
 		break;
 
 	case 1:
-		latch = ppumask.Raw;
+		data = ppumask.Raw;
 		break;
 
 	case 2:
-		latch =  ppustatus.Raw;
+		data = ppustatus.Raw;
 		ppustatus.Flag.VBlankStarted = 0;
 		addressLatch = 0;
 		break;
@@ -223,7 +224,12 @@ Byte PPU::ReadRegister(Byte id)
 		break;
 
 	case 7:
+		data = latch;
 		latch = bus->ReadPPU(ppuaddr.Raw);
+
+		if (ppuaddr.Raw >= 0x3F00)
+			data = latch;
+
 		ppuaddr.Raw += (ppuctrl.Flag.VRAMAddrIncrement ? 32 : 1);
 		break;
 	
@@ -232,7 +238,7 @@ Byte PPU::ReadRegister(Byte id)
 		break;
 	}
 
-	return latch;
+	return data;
 }
 
 void PPU::WriteRegister(Byte id, Byte val)

src/debugger/PatternTableViewer.cpp

@@ -63,6 +63,8 @@ void PatternTableViewer::DecodePatternTable(int index, std::vector<Color>& buffe
 {
 	// uint8_t stride = 128;
 	Word baseAddr = 0x1000 * index;
+	if (baseAddr >= mapper->CHR_ROM.size())
+		return;
 
 	for (int y = 0; y < 16; y++)
 	{

src/mappers/Mapper000.cpp

@@ -8,7 +8,6 @@ Mapper000::Mapper000(const Header& header, std::ifstream& ifs) :
 	Mapper(header)
 {
 	LOG_CORE_INFO("Allocating PRG ROM");
-	prgBanks = header.PrgROM;
 	PRG_ROM = std::vector<Byte>(0x4000 * prgBanks);
 	ifs.read((char*)PRG_ROM.data(), 0x4000 * prgBanks);
 

src/mappers/Mapper000.hpp

@@ -1,6 +1,5 @@
 #pragma once
 
-#include <vector>
 #include <fstream>
 #include "../Mapper.hpp"
 
@@ -16,7 +15,4 @@ public:
 	virtual Byte ReadPPU(Word addr) override;
 	virtual void WriteCPU(Word addr, Byte val) override;
 	virtual void WritePPU(Word addr, Byte val) override;
-
-private:
-	Byte prgBanks = 0;
 };

src/mappers/Mapper001.cpp

@@ -0,0 +1,126 @@
+#include "Mapper001.hpp"
+
+Mapper001::Mapper001(const Header& header, std::ifstream& ifs) :
+	Mapper(header)
+{
+	LOG_CORE_INFO("Allocating PRG ROM");
+	PRG_ROM = std::vector<Byte>(0x4000 * prgBanks);
+	ifs.read((char*)PRG_ROM.data(), 0x4000 * prgBanks);
+
+	LOG_CORE_INFO("Allocating CHR ROM");
+	CHR_ROM = std::vector<Byte>(0x2000 * chrBanks);
+	ifs.read((char*)CHR_ROM.data(), 0x2000 * chrBanks);
+}
+
+Byte Mapper001::ReadCPU(Word addr)
+{
+	if (0x8000 <= addr && addr <= 0xFFFF)
+	{
+		Byte selectedBank = prgBank;
+		Byte prgControl = (control >> 2) & 0x3;
+
+		switch (prgControl)
+		{
+		case 0:
+			selectedBank &= ~0x1;
+			break;
+
+		case 1:
+			if (addr < 0xC000)
+				selectedBank = 1;
+			break;
+
+		case 2:
+			if (addr >= 0xC000)
+				selectedBank = prgBanks;
+			break;
+		}
+
+		return PRG_ROM[addr & (0x4000 * selectedBank - 1)];
+	}
+
+	return 0x00;
+}
+
+Byte Mapper001::ReadPPU(Word addr)
+{
+	if (0x0000 <= addr && addr <= 0x1FFF)
+	{
+		Byte selectedBank = 0x00;
+		Byte chrControl = (control >> 4) & 0x1;
+
+		if (chrControl)
+		{
+			if (addr < 0x1000)
+				selectedBank = chrBank0;
+			else
+				selectedBank = chrBank1;
+		}
+		else
+		{
+			selectedBank = chrBank0 & ~0x1;
+		}
+
+		return CHR_ROM[addr & (0x1000 * selectedBank - 1)];
+	}
+
+	return 0x00;
+}
+
+void Mapper001::WriteCPU(Word addr, Byte val)
+{
+	if (addr <= 0x8000 && addr <= 0xFFFF)
+	{
+		if ((val & 0x80) == 0x80)
+		{
+			shiftRegister = 0x00;
+			control |= 0x0C;
+			return;
+		}
+
+		latch++;
+		shiftRegister >>= 1;
+		shiftRegister |= (val & 0x1) << 4;
+
+		if (latch == 5)
+		{
+			Byte registerSelect = (addr & 0x6000) >> 13;
+			switch (registerSelect)
+			{
+			case 0:	control		= shiftRegister; break;
+			case 1:	chrBank0	= shiftRegister; break;
+			case 2:	chrBank1	= shiftRegister; break;
+			case 3:	prgBank		= shiftRegister; break;
+			}
+
+			shiftRegister = 0x00;
+			latch = 0;
+		}
+	}
+}
+
+void Mapper001::WritePPU(Word addr, Byte val)
+{
+	
+}
+
+bool Mapper001::MapCIRAM(Word& addr)
+{
+	if ((control & 0x3) < 2)
+	{
+		LOG_CORE_WARN("Mapper MMC1 doesn't yet support One-Screen mirroring");
+		return true;
+	}
+
+	if ((control & 0x3) == 0x3)
+	{
+		// Shift Bit 11 into Bit 10
+		addr &= ~(1 << 10);
+		addr |= ((addr & (1 << 11)) >> 1);
+	}
+
+	// Unset bit 11
+	addr &= ~(1 << 11);
+
+	return false;
+}

src/mappers/Mapper001.hpp

@@ -0,0 +1,27 @@
+#pragma once
+
+#include <fstream>
+#include "../Mapper.hpp"
+
+class Mapper001 :
+	public Mapper
+{
+public:
+	Mapper001(const Header& header, std::ifstream& ifs);
+
+	virtual Byte ReadCPU(Word addr) override;
+	virtual Byte ReadPPU(Word addr) override;
+	virtual void WriteCPU(Word addr, Byte val) override;
+	virtual void WritePPU(Word addr, Byte val) override;
+	
+	virtual bool MapCIRAM(Word& addr) override;
+
+private:
+	Byte latch = 0;
+
+	Byte shiftRegister = 0x00;
+	Byte control = 0x00;
+	Byte chrBank0 = 0x00;
+	Byte chrBank1 = 0x00;
+	Byte prgBank = 0x00;
+};

src/mappers/Mapper003.cpp

@@ -0,0 +1,48 @@
+#include "Mapper003.hpp"
+
+#include <fstream>
+#include "../Log.hpp"
+
+Mapper003::Mapper003(const Header& header, std::ifstream& ifs) :
+	Mapper(header)
+{
+	LOG_CORE_INFO("Allocating PRG ROM");
+	PRG_ROM = std::vector<Byte>(0x4000 * prgBanks);
+	ifs.read((char*)PRG_ROM.data(), 0x4000 * prgBanks);
+
+	LOG_CORE_INFO("Allocating CHR ROM");
+	CHR_ROM = std::vector<Byte>(0x2000 * chrBanks);
+	ifs.read((char*)CHR_ROM.data(), 0x2000 * chrBanks);
+}
+
+Byte Mapper003::ReadCPU(Word addr)
+{
+	if (0x8000 <= addr && addr <= 0xFFFF)
+	{
+		return PRG_ROM[addr & (0x4000 * prgBanks - 1)];
+	}
+
+	return 0x00;
+}
+
+Byte Mapper003::ReadPPU(Word addr)
+{
+	if (0x0000 <= addr && addr <= 0x1FFF)
+	{
+		return CHR_ROM[0x2000 * selectedChrBank + addr];
+	}
+
+	return 0x00;
+}
+
+void Mapper003::WriteCPU(Word addr, Byte val)
+{
+	if (0x8000 <= addr && addr <= 0xFFFF)
+	{
+		selectedChrBank = val & 0x3;
+	}
+}
+
+void Mapper003::WritePPU(Word addr, Byte val)
+{
+}

src/mappers/Mapper003.hpp

@@ -0,0 +1,21 @@
+#pragma once
+
+#include <fstream>
+#include "../Mapper.hpp"
+
+struct Header;
+
+class Mapper003 :
+	public Mapper
+{
+public:
+	Mapper003(const Header& header, std::ifstream& ifs);
+
+	virtual Byte ReadCPU(Word addr) override;
+	virtual Byte ReadPPU(Word addr) override;
+	virtual void WriteCPU(Word addr, Byte val) override;
+	virtual void WritePPU(Word addr, Byte val) override;
+
+private:
+	Byte selectedChrBank = 0;
+};